1. Field of the Invention
The present invention relates generally to the design of analog to digital converters (ADC), and more specifically to the design and implementation of a multi-stage ADC.
2. Related Art
An analog to digital converter (ADC) receives an analog signal as input and provides (generates) a digital code corresponding to strength of the analog signal at various time instances (samples) as output. The number of bits in the generated digital code represents the resolution of the ADC. A reference signal (Vref) is often used by an ADC in providing such conversions. In general, Vref specifies the maximum input voltage (dynamic range) that can be converted into a corresponding digital code.
ADCs are often implemented in number of stages with each stage resolving a corresponding number of bits forming a sub-code. All such stages operate using a common reference in one prior embodiment. The sub-codes generated by the stages are used to generate a final digital code corresponding to the analog input. A pipelined ADC is a type of ADC which contains multiple stages with each stage resolving a number of bits. Details of a pipe line ADC is described below in further detail.
FIG. 1 is a block diagram illustrating the details of a pipe line ADC which is used to illustrate deficiencies with some prior approaches as well as various aspects of the present invention. ADC 100 is shown containing sample and hold amplifier (SHA) 110, stages 120-1 through 120-S, and digital error correction block 130. Each block is described below in further detail.
SHA 110 samples the input analog signal received on path 101 and holds the voltage level of the sample on path 111 for further processing. Digital error correction block 130 receives sub-codes from various stages, and generates a digital code corresponding to the sample received on path 111. Various error correction approaches, well known in the relevant arts, may be used to correct any errors in the received sub-codes. The generated digital code is provided on path 139 as final digital code corresponding to a input analog signal at a particular time instant.
Each stage 120-1 through 120-S generates a sub-code (based on the reference signal Vref) corresponding to a voltage level of an analog signal received as an input, and an amplified residue signal as an input to a (any) next stage. For example, stage 120-1 converts a voltage level on path 111 to generate a sub-code on path 123-1, and the amplified residue signal generated on path 112 is provided as an input to stage 120-2. A common reference signal Vref is provided to stages 120-1 through 120-S. FIG. 2 further illustrates (logical) components contained in each stage (described with reference to stage 120-1 only, for conciseness) of a pipe line ADC according to a known approach.
With respect to FIG. 2, stage 120-1 is shown containing flash ADC 250, digital to analog converter (DAC) 260, subtractor 270 and gain amplifier 280. Flash ADC 250 (an example of a sub ADC) converts a sample of an analog signal received on path 111 into a corresponding p-bit sub-code provided on path 256 (contained in path 123-1 of FIG. 1, and P is less than N). DAC 260 converts the sub-code received on path 256 into corresponding analog signal (Vdac) on path 267.
Subtractor 270 generates a residue signal as the difference of sample 111 (Vi) and the analog signal received on path 267. Gain amplifier 280 amplifies the residue signal (Vi-Vdac) and is provided on path 112 as an amplified residue signal. The signal on path 112 is used to resolve the remaining bits in the N-bit digital code by the subsequent stages of the ADC. The manner in which the sub-code and the residue signal are generated by each stage is described below with respect to FIG. 3 and FIG. 4 respectively.
Description is continued with respect to a stage generating a p+1 bit sub-code, in which 1 bit is used as redundant bit and p bits are used as effective bits in generating the N-bit digital code noted above.
FIG. 3 is a block diagram illustrating the implementation of a portion of flash ADC 250 as relevant to an understanding of the deficiencies of a prior embodiment. The block diagram is shown containing comparators 310A–310Y and resistors 330A–330Z. Each component is described below in further detail.
Resistors 330A–330Z (of equal resistance values) operates as a resistor ladder network which divides the reference voltage Vref (equal to REFP-REFM) into equal voltage steps (or corresponding threshold values) for comparison of corresponding step with the input analog voltage (differential input analog represented as InpP and InpM) by respective comparator 310A–310Y. The number of resistors used in a ladder network equals the number of comparators plus one.
Comparators 310A–310Y (2p+1 number of comparators are used in a stage providing p bit sub-code) compare the input analog signal with a corresponding threshold value generated by the resistor ladder network. The comparator output represents a output of a flash ADC 250 representing a sub-code of stage 120-1.
Continuing with respect to FIG. 4, DAC260, subtractor 270, and gain amplifier 280 are implemented using a capacitor network, switches and a operational amplifier (Op-amp). FIG. 4 is shown containing Op-amp 450, input capacitors 430A and 430B, feedback capacitors 460A and 460 B and switches 410A–410F, 480A and 480B. Each component is described below in further details.
The circuit in FIG. 4 operate in two phases. In the first phase (sampling phase) switches 410A and 410D are closed and remaining switches 410B, 410C, 410 E, 410F, 480A and 480B are kept open. As a result, input capacitors 430A and 430B stores a charge proportional to the input analog signal received on path 111.
In the second phase, switches 480A and 480B are closed and switches 410A and 410D are kept open. Switches 410B, 410C, 410 E and 410F are operated based on the output of the flash ADC 250. Switch connections are made such that the input terminals of the sampling capacitors 430A and 430B is connected either to REFP/REFM terminal or to REFCM terminal. As a result, capacitors 430A and 430B transfer a charge proportional to the difference (difference signal) of input signal and the REFP/REFM or REFCM to feedback capacitors 460A and 460B. The difference is amplified by Op-amp 450 and provided as amplified residue signal to the next stage.
The amplification factor (magnitude by which difference signal is amplified) of gain amplifier 280 is proportionate to the ratio of the capacitance values of sampling capacitor 430A (430B) and feedback capacitor 460A (460B).
However, for such amplification factor (A=2p) to be realized with a desired degree of precision, gain amplifier 280 may need to be implemented with ideal characteristics. Due to deviation from such ideal characteristics, errors are introduced and some example errors are noted below.
One source of error in achieving amplification factor (A) is that the open loop gain (D.C. gain) of op-amp 450 needs to be very high (infinity), and deviations from such high value causes bit errors. The bit error ‘e1’ caused when a closed loop gain ‘A’ is achieved using a Op-amp having DC gain of ‘G’ is given by:e1=(A*Vref)/G  Equation 1
Another source of error in achieving amplification factor (A) is the inability of op-amp 450 to settle quicky to a final amplified value, which is measured by Unity Gain Bandwidth (UGB). The UGB also ideally needs to be very high (infinite), and deviation from such high value causes bit errors. The bit error e2 caused due to a UGB of the Op-amp is given by:e2=Vref/exp(UGB*th/A)  Equation 2
wherein ‘th’ represents the hold time of the stage.
As may be appreciated, as the number of bits to be resolved by a stage increases (i.e., for a higher resolution), to keep e1 (or e2) at a desired constant value, G (and UGB) needs to be increased correspondingly. Such a requirement is often more important in early (e.g., first) stages, which generally resolve the more significant bits (MSBs).
Unfortunately, implementation of op-amps with very high G and UGB often requires more power consumption, area requirements, etc. Accordingly, it is desirable at least sometimes that the high gain requirement of op-amps be relaxed, while obtaining desired accuracy.
What is therefore needed is a multi-stage ADC architecture which addresses some of the requirements noted above.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit (s) in the corresponding reference number.